//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// M8051W/EW ALU Carry Combiner Element
// 
// $Log: m3s002dy.v,v $
// Revision 1.5  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.2  2001/10/31
// First parsable verilog for EW
//
// Revision 1.1.1.1  2001/07/17
// Re-imported E-Warp from Farnham filesystem
//
// Revision 1.4  2000/10/24
// Multiplier rewritten to improve power consumption.
// Code changes for Leonardo (ECN01372).
// Code changes for formal verification tools (ECN01410).
// MOVX @Ri page address controllable from PORT2I if I/O ports ommitted (ECN01387).
//
// Revision 1.3  2000/02/05
// Name change repercussions
//
// Revision 1.2  1999/11/30
// More debug changes.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
// Revision 1.1  1999/10/22
// Initial revision
//
////////////////////////////////////////////////////////////////////////////////

module m3s002dy (S, P, G, C_IN, C_EN);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //

  output [3:0] S;
  input  [3:0] P;
  input  [2:0] G;
  input  C_IN;
  input  C_EN;

  reg    [3:0] S;

//*********************************************************************
// This module combines ALU product/propagate (P) and carry/generate (G)
// bits to produce carry corrected result (S) of a 4-bit ALU operation
// (a carry look ahead generator).  It is instantiated separately from
// the ALU in order to prevent naive synthesis algorithms from producing
// slow ripple carry implementations of this function.

  always @ (P or G or C_IN or C_EN)
  begin: p_nibble_sum
    S[0] <= P[0] ^ C_IN;		
    S[1] <= P[1] ^ (   (C_IN && P[0]) || (C_EN && G[0]));		
    S[2] <= P[2] ^ (   (C_IN && P[0] && P[1]) || (C_EN && P[1] && G[0])
                                           || (C_EN && G[1]));
    S[3] <= P[3] ^ (   (C_IN && P[0] && P[1] && P[2])
                    || (C_EN && P[1] && P[2] && G[0])
                    || (C_EN && P[2] && G[1]) || (C_EN && G[2]));
  end		

endmodule
